Counter

TEA has some iterations to do multiple rounds of mixing and shuffling the data values.  To achieve this, we'll use some looping.  There are only 64 rounds, so were this algorithm designed for hardware, we might be able to unroll them into 64 parallel operations.  But, this algorithm was designed for software and it seems very little parallelism can be enlisted to speed things up.  The results of each round feedback into the previous.  Feedback loops like this are important for good mixing and permuting.  Also, since this is a Feistel cipher, half of the data block is mixed/shuffled with the other half.  Each round jumbles and mixes from one side to the other.  This dependency makes parallelization very difficult at very best to impossible.  I imagine determining any required structure or method to parallelize this is equivalent to cryptanalizing it.   Finding a usable result would probably crack it.

So, since we need to iterate, we need a counter.  Below is a counter implemented with a 32bit adder, a 32bit  register/memory and an extra chooser to feed the value 0 in when the reset signal is sent.  The 7 segment decoder + display is just for debugging.

The inc signal increments the counter.  Reset sets it to 0.  q is the output.  I forgot to change the output name, but it is the only one, so it doesn't really matter.  I'm not sure why 'q' is the default.  Maybe it is some standard.