Decoding and Processing Instructions

Even though this is an ASIC for a very specific algorithmic operation, I'm going to implement it similarly to a general purpose computer with a very limited instruction set.  Well, actually, I don't really know how to implement a general purpose computer, so, like everything else here, this is my best guess.  Coming from a software background, these implementations are just my naive imaginings of how this might be done in hardware.  Certainly someone with a Computer Engineering or Electrical Engineering background will have learnt this in school or from work and know the optimal ways to get these things running.  Nonetheless, it's fun to experiment, right!?!

First, I threw some registers and ROM together to think about what I want the instruction set to look like.  The idea is to have the program live in ROM, some registers that map more or less to the algorithm with some more or less general purpose places for different bits of data.

I'll show you the general high level layout, and then dig into some specific regions.  Here is the high level view:

A. is the main state driver which consists of a counter for the current instruction and what I call a "multi-stager" that moves through substates of executing the instruction.  To the bottom of A are 3 ROMs which contain the instructions divided up into lists of Opcode, Operand A and Operand B.  I could have made it a single ROM with both opcodes and operands, but thought this would be easier for now.

B. is the input data with the key and data.  They are ROM now, but I'll change them to RAM since when this part would be called, there would be some lines to load the values in and then eventually a line for the 32biy result.  I haven't done the result yet.

C. has the Key registers that get loaded with the key for use during the encryption.

D. has some general purpose processors with R5 and R6 normally containing the V0 and V1 variables.

E.  is the machinery to handle the decoding of the instruction 0 - Load Constant into Register.  I used an "all-low" comparator to activate it.  That was before I made the "32bit router" part.  I'll switch it soon.

F. is the machinery for handling the instruction 1 - Load memory at index into register.

I'll post more about details of each as well as the instruction set and some of the initial program.